3 Li, H Gwee, BH Chang, JS Tan, MT 2000 Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on 1 514-517 08/08/2000 0-7803-6475-9 amplifiers, harmonic distortion, low-power electronics, pulse width modulation, sampling methods A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=951696